This invention relates generally to a system and method for managing access to common resources in a multiprocessor system wherein it is desirable to provide the fastest access by the processors to the common resources.
When a particular application/project/job requires more processing power than a single processor is capable of providing, it becomes necessary to provide a coprocessor, such as a digital signal processor (DSP) or a floating point unit (FPU). Thus, the tasks associated with the particular application are handled in unison by the main processor and the coprocessor. The most common conventional solution to solving the problem of how to allocate the resources to the multiple processors is to utilize a dual-ported memory subsystem wherein each processor has equal access to the common resources that may be used by both processors. Alternatively, each processor may be provided with a dedicated resource and a mechanism for transferring commands and data through a shared “Mail Box”. The shared “Mail Box” typically includes a number of first in first out (FIFO) registers of various lengths.
The conventional dual-ported memory solution provides processor independent design implementation, but requires a large amount of hardware for the random access arbitration for both processors. Consequently, the actual implementation of the arbitration logic and the random access for the common bus creates more delay on the common resources since the access to the common bus must be determined prior to accessing the common resources. The typically small degradation in the access speed in the dual-ported memory gets magnified by a significant amount when that common resource is the main memory because the main memory is the common resource most utilized by both processors. Therefore, the interdependency of the multiple processors increases since they both rely heavily on the main memory.
The conventional dedicated resource for each processor with the shared “Mail Box” scheme prevents the multiple processors from competing with each other for the same resource, but suffers greatly in terms of access speed since the data and commands must all pass through the “Mail Box” which has a relatively narrow throughput. In addition, duplicative resources are necessary since each processor has its own dedicated resources. Although the scheme works quite well when the tasks for the processors are well defined and common data transfer is relatively small, the actual performance and resource utilization suffers greatly when the tasks are not well defined and the processors are therefore more interdependent.
In another conventional system for sharing common memory between one or more processors, the memory has gate logic associated with each processor and each bit in the memory has two access points (e.g., one access point for the first processor and one access point for the second processor for a two processor system). In this configuration, the contention between the processor is reduced since each processor has its own access to each bit of memory. The drawback with this approach is that there is large amount of duplicated logic, including the read and write logic, to control the accesses by each processor. In addition, each memory cell is more complex than a typical memory cell. In particular, a typical DRAM memory cell has a single transistor and a capacitor whereas the memory cell for the dual access port memory has four transistors for each cell since each cell may be accessed independently by the first or second processor.
Thus, it is desirable to provide a cross bar multipath resource controller that overcomes the above limitations and problems with conventional multiprocessor resource management solutions and it is to this end that the present invention is directed.